In mobile systems-on-a-chip (SOC), chip performance is becoming increasingly important to benchmark against competition. The traditional approach is to design an integrated circuit using transistor models and simulate it at certain voltage, temperature, and process corners to ensure the integrated circuit meets certain performance criteria. Once design is complete, the integrated circuit is manufactured according to the transistor specifications used by the design. Thus, the performance of the integrated circuit is fixed at the design operating conditions. However, customers always demand a higher performance product. Thus, it is highly desirable to produce an integrated circuit that provides higher performance than a competitor's product, to differentiate the integrated circuit from the competitor's product. Conventional methods dictate that integrated circuit improvement requires redesigning the entire integrated circuit. However, redesigning the entire integrated circuit requires very high engineering costs and long cycle times. What is needed are integrated circuit design and fabrication techniques that allow for future performance enhancement of portions of the integrated circuit without sacrificing standby (i.e., sleep-mode) leakage, and without requiring redesign of the entire integrated circuit.
Accordingly, there are long-felt industry needs for methods and apparatus that mitigate problems of conventional methods and apparatus, including a design method to enable selective push processing push during manufacturing to improve performance of selected circuits of a system-on-a-chip integrated circuit.